Transistor switching circuit



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United States Patent O 3,546,492 TRANSISTOR SWITCHING CIRCUIT Donald .I.Barcliok, Chicago, Ill., assignor to Admiral Corporation, Chicago, Ill.,a corporation of Delaware Filed Oct. 10, 1967, Ser. No. 674,237

Int. Cl. H03k 3/26 U.S. Cl. 307-300 7 Clalms ABSTRACT F THE DISCLOSURE Acircuit arrangement for speeding up the actual switching time of atransistor including an inductance in series with the drive pulse sourceand the base-emitter junction of the transistor. The inductance controlsthe ow of base current during switching so that reverse base currentflows over the entire period of collector current decay.

This invention is concerned with transistor switching times and, inparticular, with switching times of transistors used in the horizontaloutput stages of television receivers. During the inevitabletransistorization of television receivers utilizing vacuum tubes, it wasrecognized that certain functions would present problems far greaterthan those normally encountered in audio and small signal circuits. Inparticular, that of developing the deflection currents for thetelevision receiver imposed stringent requirements on transistorcharacteristics and circuit design. Ay major problem has been topreclude the likelihood of breakdown of the semiconductor junctions ofthe transistors due to overheating, voltage punch through, etc., withoutnecessitating extremely rigid and uneconomical transistor tolerances.

The art of transistor manufacture is rapidly approaching a high level ofrefinement. Similarly, the mechanics of semiconductor charge movement,barriers, storage times and the like are being constantly studied, andphysical explanations of the empirically observable phenomena set forth.However, there is much that is unexplained in transistor operation, andconsequently, many observable results are as yet only explainable on thebasis of hypotheses. Recognizing that our knowledge of semiconductorphysics is growing constantly, it will be understood that any particulartheory advanced by way of explanation of the invention is not to beconsidered conclusive. Rather, the invention will be describedempirically and any theories advanced in support of the observedphenomena are solely for simplifying an understanding of thesephenomena.

A major problem in transistor switching circuits occurs during actualswitching, that is when the collector current is rapidly falling and thecollector Voltage rapidly rising. It is this problem to which thepresent invention is directed.

In the art, the terms storage time and fall time are generally used inspecifying transistor parameters. Storage time is the time intervalbetween base current reversal (below zero level) until the collectorcurrent has declined 10%. Fall time is that time required for thecollector current to decline from its 90% value to its 10% value. Forthe purposes of explanation of this invention, the area of interest isthe entire interval from the beginning of the switching operation, thatis when the collector current just begins to decline, to the point whenthe collector current actually reaches zero.

This interval will be called the cutoff time for the collector current.

The slope of collector voltage rise 'is primarily a function of theconnected load on the transistor. For practical purposes, this slope ofcollector voltage is relatively unchanged with the circuit of theinvention and need be considered in our discussions only to the extentthat it is an indispensable element. in the switching problem. The cruxof the problem lies in the fact that the transistor collector current isswitched so slowly that a substantial overlap period exists during whichthe transistor collector voltage and current are relatively large. Thiscondition leads to excessive junction heating, and the transistorperforms as a relatively poor switch. During the actual circuit designof a horizontal output stage, a large number of transistors experiencedthermal runaway and ultimate destruction as a result of excessiveheating during switching.

The classical solution of increasing the reverse base current, i.e.,driving the transistor harder into cutoff, did not significantly affectthe problem. The conventional base speed up capacitor was also triedwith somewhat better results, although the large parallel resistancerequired across the capacitor added considerably to the base powerrequirements. The solution surprisingly was that of tailoring the basecurrent so that reverse base current would flow for the entire cutofftime of the collector current. It was found that, when this conditionprevailed, the collector current cutoff time was optimum (shortest) forthe given transistor, and consequently, the period of simultaneouslyexisting large collector current and collector voltage was minimized.Using this technique results in a small delay in initiating switching(appears as an addition to storage time), but of such slight duration asto be unobjectionable. In accordance with the invention, it was foundthat the simple addition of an inductive element in series with thedriving pulse source and the transistor base-emitter junction proved acomplete solution of the problem.

Accordingly, a principal object of this invention is to provide animproved switching transistor circuit arrangement.

A further object of this invention is to provide a methodfor determiningthe optimum operating conditions for a switching transistor.

Another object of this invention is to provide a switching transistorcircuit arrangement utilizing a small inductive element in thetransistor input circuit to control the flow of base current theretoduring switching.

A still further object of this invention is to provide a method ofvisually determining the optimum operating conditions of a switchingtransistor which method employs the use of an adjustable inductanceelement and an oscilloscope.

Other objects and features of this invention will become apparent upon areading of the following specication in conjunction with the drawings inwhich:

FIG. l is a partial, schematic diagram of a television horizontaldeflection circuit utilizing a switching transistor incorporating thecircuit of the invention; and

FIGS. Zal-2c represent graphical portrayals of circuit switchingconditions with which the invention is concerned.

Referring now to FIG. l, there is shown a driver transistor 10 which hasa base input circuit supplied with a substantially square wave voltagefor switching.

The output load of transistor includes the primary winding of a drivertransformer. The driver transformer has a secondary winding 16 connectedin series with the base-emitter circuit of output transistor 20.

The output transistor, in this environment supplying the horizontaldeflection power for a television receiver, has an emitter electrode 21,a base electrode 22, and a collector electrode 23. Collector 23 issupplied operating potential from a source of B-lvoltage through aportion 32 of a conventional autotransformer. A coupling capacitor 27 isconnected from collector 23 to a yoke 35 conventionally mounted on theneck of the picture tube, not shown. The yoke is responsible fordeveloping the necessary magnetic fields for scanning the electron beamover the face of the picture tube screen. As shown in the drawing,`onepair of yoke deflection coils are connected to the horizontal outputcircuit and another pair to a vertical output circuit (not shown). Adamper diode 2S is connected across the collector and emitter electrodesof transistor and performs the conventional function in thereaction-scan process of rectifying the ringing pulse produced uponcollapse of the yoke eld and producing a portion of the scanning currentfor yoke 35. The capacitor 26 is used for tuning purposes, alsowell-known in the art. A high voltage developing winding 33 of theautotransformer is connected to a high voltage rectifier diode 34,lwhich as indicated, is connected to the picture tube, not shown.

In prior art circuits, secondary winding 16 would be generally connectedto emitter' 21 directly. However, in the instant circuit, an inductor30, parallelled by a resistor 31, is serially interposed between winding16 and emitter 21 for purposes which will be explained shortly. Resistor31 is included for damping purposes and should not be considerednecessary in practicing the invention.

In operation, the square wave voltage input to driver transistor 10results in switching voltage being developed at the base of horizontaloutput transistor 20 which, in accordance with well-known techniques,further results in large voltage pulses in the output circuit oftransistor 2.0 due to the reaction-scan deflection system. The pulsevoltages occur across the essentially inductive yoke circuit and asaw-tooth current essential for linear deflection of the electron beamacross the picture tube screen occurs lwhen transistor 20 is in asaturated state.

In transistor switching circuits (which generally involve a transistorbeing driven from a saturated condition to a cutoff condition and viceversa), finite times are required between the drive signal change andthe transistor response. These time intervals or delays should not beconfused with normal time constants of circuitry coupled to thetransistor, but represent delays inherent in the device itself. lInother words, the transistor does not react instantaneously to inputsignal or driving signal changes. It is also known that a transistor inheavy saturation requires a longer time to switch into cutoff than onewhich is lightly in saturation. As alluded to briefly above, variousterms have been developed to describe these different characteristics,among the most important of which is storage time, also defined as thattime required yfor stored minority charge to become zero, fall time anddelay time.

In general, the switching time for a transistor being turned oncomprises a delay time due to charging of the transistors inherentcapacitances plus a rise time, generally determined by the load circuitconnected thereto. The delay time is characteristically defined as thetime required for the collector current (Ic) to reach 10% of its steadystate Value and the rise time, that required for Ic to go from its 10%value to a 90% value. Conversely, the off time of the transistor isdefined as a combination of storage time and fall time, previouslydiscussed. The storage time is generally believed to be due to an excessof minority carriers in the base junction region of the transistor whichmust be removed before 4 the junction becomes normally responsive. Thefall time, like the rise time, is defined as that interval required forthe collector current to decline from its value to 10% of its steadystate value.

In transistors, it is essential to establish a base charge (that is, anexcess of minority carriers in the region of the base-emitter junction),in order to establish a collector current. In fact, the collectorcurrent is not only determined by the excess minority carrierscomprising the base charge, but actually equals this excess charge.Normally, the excess minority carriers are injected into the emitter anddiffuse across the base-emitter junction. Upon reaching theemitter-collector junction, they become the collector current. Thus, thecollector current is substantially equal to the emitter currentexcepting a small percentage of these 4minority carriers lost in thebase region.

Thus, it becomes clear that if a collector current is to .beestablished, a base charge must be established and likewise, if thecollector current is to be terminated, this base charge must be removed.The magnitude of the base charge is, of course, a function of the degreeof saturaof the transistor. Thus, it also seems obvious that a heavilysaturated transistor would be more dicult to turn off (more excess basecharge to be removed) than a lightly saturated transistor.

Conventionally, storage time is that time required to remove theseexcess base chasges whereas delay time is the time to establish theexcess base charge. Following this, it would appear that the storagetime could be reduced by heavily reverse biasing the transistor andthis, in general, is true. However, it has been found that storage time,as defined, does not yield a true picture of what is occurring withinthe thansistor. The period Iafter storage time which includes andextends beyond fall time and which might loosely be considered atransition time before the transistor is actually cut 01T, is thecritical period in heavy current switching applications. It is duringthis period that simultaneously occurring collector currents andpotentials cause excessive heating of the junction. Merely increasingthe reverse drive has little effect on this period.

In FIG. 2a, there is graphically portrayed curves of collector current,collector voltage, and base current of a typical switching transistordriving an inductive load. These curves are generally indicative of theprior art and are appropriately labelled. The indicated quantities areshown on the small schematic representation of the circuit at the rightof the graphs in FIGS. 2a and 2b. A full period of operation is notshown, but merely an expanded view of the critical portion of the cycle,namely that occurring during switching of the transistor from asaturated to a cutoff condition. As shown, the collector current isgenerally increasing when the base drive current is reversed. Thiscorresponds to the saturated transistor being heavily reverse biased.The curves indicate the fall of collector current and the simultaneousrise of collector voltage, with the dotted area showing the overlapperiod, that is the period when the junction is dissipating an abnormalamount of power. It will be noted that for FIG. 2a, a relatively longperiod exists when sizeable collector current and collector voltages arepresent. This corresponds to a circuit where the base-emitter junctionof the transistor is directly connected across the driving the transfformer secondary.

In FIG. 2b, a similar set of curves is shown for a circuit identical tothat used in FIG. 2a with the exception of an inductive element beinginserted between the baseemitter junction and the driving source. Theinductance exerts a control on the base current as shown andsubstantially precludes the rapid change thereof. Hence, instead of thebase junction being heavily reverse biased in a rapid manner the basejunction is subjected to a slowly diminishing current which graduallyreverses as shown. This type of switch yields the surprising result ofdelaying somewhat the beginning of the collector current deeline, butcausing an accelerated decline thereof once the decline begins. Theperiod of overlap between the collector current and collector voltage isseen to have been materially diminished due to the rapid decline ofcollector current, and consequently, the transistor junction dissipatesja much smaller amount of energy than in the previous example.

In the embodiment shown, the forward base current fall and reverse basecurrent rise is controlled by the inductive reactance in series with thebase. Although the forward base current is reduced slowly to zero, thereis little effect on the rising collector current. This indicates anexcess of minority carriers. in the base region which are supplyingcollector current during base current fall. Since carriers are beingdepleted during the base fall interval, the device is better prepared tobe turned off at base current reversal.

In the case where the base current is reversed rapidly and'at greatermagnitude, the collector current cutoff time is appreciably greater.This slower cutoff is the re sult of what in the art has been termedtrapped carriers. These carriers apparently are not close enough to thebase-emitter field to be sufficiently attached and hence removed, andonly can be depleted by recombination, which is a relatively slowprocess. By delaying and slowing down reverse base current, and causingit to flow during the entire cutoff time, these carriers are acted uponfor a longer time which therefore results in an appreciable speedup ofcollector current cutoff.

In FIG. 2c, there is shown an overlay of the curves of FIGS. 2a and 2bas well as an additional set of dotted curves covering an intermediatecondition. The curves have been displaced in time slightly to initiatecollector current decline at approximately the same time for readilycomparison of the lc slopes. In this figure, a solid line indicates thecurrent circuit with the inductance being optimized for minimumcollector current cutoff time. The dashed line indicates the circuitpreviously discussed with reference to FIG. 2a.' where no inductance isincluded. The dotted curves display conditions where the reverse currentIBZ is caused to flow for a longer period of time than that shown inFIG. 2a, but for a shorter period of time than that shown in FIG. 2b.Noting the respective areas of overlap of' collector current andcollector voltage, it will be readily perceived that the optimumswitching of the transistor is obtained when the reverse base current Imis caused to fiow for the full period of collector current cutoff. Ithas further been found that increasing the value of the inductancebeyond the optimum point does not shorten the collector current cutofftime, but merely slows down the entire switching operation. If theinductance is made too large, it will be found that the transistorPbegins to come out of saturation prior to switching, which is notacceptable. L

While, no doubt, the optimum value of inductance required for any givencircuit configuration may be calculated from a full knowledge of Vallparameters involved, by far a much simpler, yet highly effective methodis to employ a variable inductance and note the resulting switchingwaveforms on an oscilloscope. It is a relatively simple matter ofadjusting the inductance to a value satisfying the criterion ofmaintaining reverse base current flow for substantially the full periodof collector current cutoff. Thereafter, the inductance value may bemeasured and this value inserted in production circuits `Without theneed for further adjustment. Thus, while a novel circuit hasbeendisclosed, it should also be recogized that a relatively simplemethod of empirically determining the optimum conditions for operatingthe switching transistor is also disclosed.

It is to be understood that the above description of a preferredembodiment of this invention is given by way of example only and thatnumerous modifications may be made without departing from the scope ofthis invention as claimed in the following claims.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

1. In combination; a transistor having an input circuit including asemiconductor junction and an output circuit; means supplying operatingpotentials to said transistor; a source of input switching voltageconnected to said input circuit and characterized by :a first portionforward biasing said semiconductor junction and a second portion reversebiasing said semiconductor junction; said transistor having an outputcircuit current cutoff delay time resulting from the effect of storedcharge in the region of said semiconductor junction and, consequently,experiencing an output circuit current decline and voltage rise ofrespective magnitudes increasing the power dissipation of saidtransistor during switching; and means including a series connectedinductor said input circuit minimizing the effect of said stored chargewhereby the slope of the output current decline is increased to precludethe simultaneous occurrence of output voltage and output current ofexcessive magnitude.

2. The combination set forth in claim 1, wherein said last mentionedmeans maintains reverse current flow through said semiconductor junctionduring said second portion of said switching voltage substantiallyduring the period required for said output circuit current to fall tozero.

3. The combination as set forth in claim 1, wherein the inductivereactance of said series connected inductor resists any abrupt changefrom said first portion to said second portion of said switchingvoltage, thereby gradually diminishing the flow of forward conductioncurrent through semiconductor junction and providing for the flow ofreverse current through said semiconductor junction substantially overthe entire period of output current decline.

4. The combination as set forth in claim 3, wherein said seriallyconnected inductor in circuit with said semiconductor junction, has avalue approximating that value which produces the shortest total declinetime for the output current of said transistor.

5. The method of optimizing operating parameters of a switchingtransistor designed to be driven heavily into collector currentsaturation and rapidly into collector current cutoff by minimizing thecutoff time of the collector current comprising the steps of: providingan inductive impedance element in series with the emitter-base junctionof said transistor; and selecting a value for said inductive impedanceelement which permits reverse base current fiow through said junctionsubstantially for the period of time during which the collector currentflows when being driven into cutoff.

6. The method of claim 5 including the additional steps of: providing aswitching voltage having a first portion heavily biasing theemitter-base junction of said transistor to produce collector currentsaturation and a second portion rapidly reverse biasing the base-emitterjunction of said transistor; providing a variable inductance in serieswith said switching voltage and said baseemitter junction; and adjustingsaid variable inductance to produce a reverse base-current in saidtransistor which ows substantially for the period of time during whichsaid collector current flows when said transistor is switched intocutoff.

7. In combination; a transistor having an input circuit including abase-emitter semiconductor junction and an output circuit; meanssupplying operating potentials for said transistor; a source of inputswitching voltage connected across said emitter-base junction andcharacterized by a first portion heavily forward biasing said junctionto produce a state of saturation in. said transistor and a secondportion reverse biasing said junction into cutoff;

said transistor having a collector current cutoff time and a collectorvoltage rise time of respective magnitudes producing excessive powerdissipation in said transistor during switching due to the effect ofstored charges in the region of said junction; and inductive means inseries circuit with said source of switching voltage and said junctionfor controlling the slope of the reverse base current produced in saidjunction such that said reverse base current flows during the entiretime interval required for said collector current to fall to zero duringswitching, thus establishing the optimum switching time for saidtransistor.

References Cited UNITED STATES PATENTS 2,933,642 4/1960 Marley 307-3002,963,592 12/1960 De Graff 307-300 3,081,437 3/1963 Radcliffe 307-300DONALD D. FORRER, Primary Examiner B. P. DAVIS, Assistant Examiner U.S.C1. X.R. 307-248, 254

